On Known-Plaintext Attacks to a Compressed Sensing-based Encryption: A Quantitative Analysis

Despite the linearity of its encoding, compressed sensing may be used to provide a limited form of data protection when random encoding matrices are used to produce sets of low-dimensional measurements (ciphertexts). In this paper we quantify by theoretical means the resistance of the least complex form of this kind of encoding against known-plaintext attacks. For both standard compressed sensing with antipodal random matrices and recent multiclass encryption schemes based on it, we show how the number of candidate encoding matrices that match a typical plaintext-ciphertext pair is so large that the search for the true encoding matrix inconclusive. Such results on the practical ineffectiveness of known-plaintext attacks underlie the fact that even closely-related signal recovery under encoding matrix uncertainty is doomed to fail. Practical attacks are then exemplified by applying compressed sensing with antipodal random matrices as a multiclass encryption scheme to signals such as images and electrocardiographic tracks, showing that the extracted information on the true encoding matrix from a plaintext-ciphertext pair leads to no significant signal recovery quality increase. This theoretical and empirical evidence clarifies that, although not perfectly secure, both standard compressed sensing and multiclass encryption schemes feature a noteworthy level of security against known-plaintext attacks, therefore increasing its appeal as a negligible-cost encryption method for resource-limited sensing applications.Comment: IEEE Transactions on Information Forensics and Security, accepted for publication. Article in pres

Low-complexity Multiclass Encryption by Compressed Sensing

The idea that compressed sensing may be used to encrypt information from unauthorised receivers has already been envisioned, but never explored in depth since its security may seem compromised by the linearity of its encoding process. In this paper we apply this simple encoding to define a general private-key encryption scheme in which a transmitter distributes the same encoded measurements to receivers of different classes, which are provided partially corrupted encoding matrices and are thus allowed to decode the acquired signal at provably different levels of recovery quality. The security properties of this scheme are thoroughly analysed: firstly, the properties of our multiclass encryption are theoretically investigated by deriving performance bounds on the recovery quality attained by lower-class receivers with respect to high-class ones. Then we perform a statistical analysis of the measurements to show that, although not perfectly secure, compressed sensing grants some level of security that comes at almost-zero cost and thus may benefit resource-limited applications. In addition to this we report some exemplary applications of multiclass encryption by compressed sensing of speech signals, electrocardiographic tracks and images, in which quality degradation is quantified as the impossibility of some feature extraction algorithms to obtain sensitive information from suitably degraded signal recoveries.Comment: IEEE Transactions on Signal Processing, accepted for publication. Article in pres

Rakeness-Based Compressed Sensing of Multiple-graph Signals for IoT Applications

Signals on multiple graphs may model IoT scenarios consisting of a local wireless sensor network performing sets of acquisitions that must be sent to a central hub that may be far from the measurement field. Rakeness-based design of compressed sensing is exploited to allow the administration of the tradeoff between local communication and the long-range transmission needed to reach the hub. Extensive Monte Carlo simulations incorporating real world figures in terms of communication consumption show a potential energy saving from 25% to almost 50% with respect to a direct approach not exploiting local communication and rakeness

A Non-conventional Sum-and-Max based Neural Network layer for Low Power Classification

The increasing need for small and low-power Deep Neural Networks (DNNs) for edge computing applications involves the investigation of new architectures that allow good performance on low-resources/mobile devices. To this aim, many different structures have been proposed in the literature, mainly targeting the reduction in the costs introduced by the Multiply and Accumulate (MAC) primitive. In this work, a DNN layer based on the novel Sum and Max (SAM) paradigm is proposed. It does not require either the use of multiplications or the insertion of complex non-linear operations. Furthermore, it is especially prone to aggressive pruning, thus needing a very low number of parameters to work. The layer is tested on a simple classification task and its cost is compared with a classic DNN layer with equivalent accuracy based on the MAC primitive, in order to assess the reduction of resources that the use of this new structure could introduce

Rakeness-based Compressed Sensing of Surface ElectroMyoGraphy for Improved Hand Movement Recognition in the Compressed Domain

Surface electromyography (sEMG) waveforms are widely used to generate control signals in several application areas, ranging from prosthetic to consumer electronics. Classically, such waveforms are acquired at Nyquist rate and digitally transmitted trough a wireless channel to a decision/actuation node. This causes large energy consumption and is incompatible with the implementation of ultra-low power acquisition nodes. We already proposed Compressed Sensing (CS) as a low-complexity method to achieve substantial energy saving by reducing the size of data to be transmitted while preserving the information content. We here make a significant leap forward by showing that hand movements recognition task can be performed directly in the compressed domain with a success rate greater than 98 % and with a reduction of the number of transmitted bits by two order of magnitude with respect to row data

A fully CMOS true random number generator based on hidden attractor hyperchaotic system

AbstractLow-power devices used in Internet-of-things networks have been short of security due to the high power consumption of random number generators. This paper presents a low-power hyperchaos-based true random number generator, which is highly recommended for secure communications. The proposed system, which is based on a four-dimensional chaotic system with hidden attractors and oscillators, exhibits rich dynamics. Numerical analysis is provided to verify the dynamic characteristics of the proposed system. A fully customized circuit is deployed using 130 nm CMOS technology to enable integration into low-power devices. Four output signals are used to seed a SHIFT-XOR-based chaotic data post-processing to generate random bit output. The chip prototype was simulated and tested at 100 MHz sampling frequency. The hyperchaotic circuit consumes a maximum of 980 \upmu μ W in generating chaotic signals while dissipates a static current of 623 \upmu μ A. Moreover, the proposed system provides ready-to-use binary random bit sequences which have passed the well-known statistical randomness test suite NIST SP800-22. The proposed novel system design and its circuit implementation provide a best energy efficiency of 4.37 pJ/b at a maximum sampling frequency of 100 MHz

A Unified Design Theory for Class-E Resonant DC–DC Converter Topologies

Resonant and quasi-resonant dc-dc converters have been introduced to increase the operating frequency of switching power converters, with advantages in terms of performance, cost, and/or size. In this paper, we focus on class-E resonant topologies, and we show that about twenty different architectures proposed in the last three decades can be reduced to two basic topologies, allowing the extension to all these resonant converters of an exact and straightforward design procedure that has been recently proposed. This represents an important breakthrough with respect to the state of the art, where class-E circuit analysis is always based on strong simplifying assumptions, and the final circuit design is achieved by means of numerical simulations. The potentialities of the proposed exact methodology are highlighted by realistic circuit-level simulations, where the desired waveforms are obtained in one single step without the need of a time-consuming iterative trial-and-error process

Through-The-Barrier Communications in Isolated Class-E Converters Embedding a Low-k Transformer

In a recent paper, a through-the-barrier communication technique suitable for isolated resonant converters has been proposed. The approach is capable of sending data bidirectionally at high speed (one bit for each converter clock period) without the need of any additional isolating device other than the transformer necessary for the power transfer, and has been demonstrated by means of a proof-of-concept low-frequency prototype. In this paper we review that work under the assumption of increasing the operating frequency by using a coreless transformer presenting low losses, but also a low coupling factor k. This allows to increase the efficiency of the converter to a very high value (92% in the proposed design working at 6.78 MHz), but the communication speed has to be reduced (one bit every four clock cycles)

A 65nm continuous-time sigma-delta modulator with limited OTA DC gain compensation

This paper explores the effects of compensating the performance degradation in high-speed Continuous-Time Sigma-Delta modulators when the loop integrators are implemented through limited gain Operational Transconductance Amplifiers. Yet, the low DC-gain strongly affects both integrator magnitude and phase responses, with a reduction in the overall effective number of bits. This work models the degradation as due to a signal-dependent memory-less perturbation and theoretically studies its compensation by feeding an opposite signal back to the integrator input. The implementation and experimental results on a 65nm CMOS 2nd order prototype evaluate the performance increase with this technique, where no other compensation, nor any digital calibration, is included. Tested in different conditions, the compensated prototype improves more than 1.5 bit the ENoB with respect to the uncompensated counterpart. For a sampling frequency of 500 MHz the power consumption is 1.7mW, resulting in a 477.2fJ/conv-lev Walden and a 148.8dB Schreirer Figures of Merit